Thermal putty or thermal pad, which is better? Myths about thermally conductive materials, thermal conductivity and temperatures

1 - Overview and Introduction 2 - The real Chain of thermal Resistances 3 - The Benefits of a cooling Backplate 4 - All what you need is a better Cooling!

Unfortunately, the chain of thermal resistances is quite complex

I deliberately carried out this investigation as part of the database update for my thermal models in order to be able to use the most realistic and practical boundary conditions possible in future simulations. The resistances in the DrMOS itself and in the circuit board should no longer just be roughly estimated, but should be available in a form that matches the real measured temperatures on the graphics card and can be directly integrated into the simulation chain.

The result is a clearly structured resistance chain for the MP87993 from Monolith. Two main paths branch off from the junction. The path leads upwards via the internal resistor ΨJT towards the top of the housing, then through the TIM on the top and on through the heatsink to the cooling medium. This path has a relatively high resistance because the plastic coating of the package accounts for the largest proportion at around 15 K/W and the pad itself only contributes a comparatively small additional resistance of around 3.3 K/W at a thickness of 0.5 millimetres and 6 W/mK thermal conductivity.

The second path runs downwards via the internal resistance ΨJB of around 2 K/W into the base pad, from there into the copper surfaces of the PCB, through FR-4 and vias to the rear and finally through convection and radiation into the ambient air. At around 3 K/W, this board path is significantly lower than the top side path, which is why around 80 percent of the DrMOS power dissipation flows into the PCB and only a small proportion goes upwards! I will now describe the whole chain again in DEtail and also break down the lower part, which I only use as a constant in the database. But for further understanding we need this now (unfortunately).

For a better understanding of the order of magnitude, the PCB section can now be divided into three symbolic sections, which together result in the approximately 3 K/W mentioned. Directly below the DrMOS, the front copper layer with its busbars and large polygonal planes ensures the initial distribution of heat, followed by the transition through the FR-4 and the vias with the highest individual proportion, and finally the transition to the rear side and local convection. The absolute number of each section is of course dependent on the component and layout, but the total plausibly represents the real hotspot situation observed on the rear side. The overview drawing of the resistance chain then looks like this:

At the top, the path from the junction via ΨJT, the topside pad and the heatsink to the cooling medium is shown. Below you can see the path via ΨJB into the bottom pad, from there into the front copper layer, on through FR-4 and vias to the rear side and finally via the rear side junction into the air.

Calculating the resistance chain

I now sit down once again on the stairs of the construction wagon and assume that, as in the previous example, around 5 watts of power dissipation are generated per DrMOS and that the 40 °C describes the already heated heatsink in this DrMOS zone, i.e. the thermal reference point for the upper path. The internal resistors and the putty remain unchanged, only the boundary conditions change. For a single MP87993 with 5 watts and a cooler at 40 °C, the following results with the values already applied

ΨJT ≈ 15 K/W
ΨJB ≈ 2 K/W
R_TIM ≈ 3.33 K/W
R_sink ≈ 1 K/W
R_board ≈ 3 K/W

first again the total resistance of both paths in parallel

R_top = ΨJT R_TIM R_sink ≈ 19.33 K/W
R_bot = ΨJB R_board ≈ 5 K/W

R_ges = (R_top – R_bot) ÷ (R_top R_bot) ≈ 3.97 K/W

At a power loss of 5 watts, the junction is then around ΔT_j ≈ 5 W – 3.97 K/W ≈ 19.9 K above the 40 degree heat sink, i.e. at around 60 °C. The power distribution remains unchanged due to the ratio of the resistances, with around 20 percent going up and around 80 percent going down. Numerically, this means

P_up ≈ 1.03 W
P_down ≈ 3.97 W

This can be used to calculate the node temperatures. From the die to the top of the housing via ΨJT

ΔT_j→top ≈ 1.03 W – 15 K/W ≈ 15.4 K

so the housing surface is approximately

T_top ≈ 60 °C – 15.4 K ≈ 44.5 °C

Over the putty with 3.33 K/W, the temperature drops again by approx

ΔT_TIM ≈ 1.03 W – 3.33 K/W ≈ 3.4 K

to around 41 °C, then via R_sink with around 1 K/W by a good 1 K to the specified 40 °C of the heat sink. On the board side, from the barrier layer to the PCB via ΨJB

ΔT_j→board ≈ 3.97 W – 2 K/W ≈ 8 K

The local VRM zone of the PCB is therefore approx

T_board ≈ 60 °C – 8 K ≈ 52 °C

A further 12 K is lost via R_board with 3 K/W at 3.97 W, so that this path also returns to the 40 °C of the thermal reference point. For a single MP87993 with 5 watts and an air cooler whose heatsink is at around 40 °C, this results in an approximate junction temperature of around 60 °C, around 44 to 45 °C on the top of the housing and around 52 °C local PCB temperature in the immediate VRM zone. Things get interesting with six DrMOS in the immediate vicinity. The relative proportions do not change at first, as the ratio of R_top to R_bot remains the same. Around 1 watt per component continues to go upwards towards the heatsink and just under 4 watts downwards into the PCB. For all six components together, this means around 6 watts into the cooler via the putty and package tops and around 24 watts into the PCB.

If the 40 °C is understood as the already measured or simulated temperature of the heat sink under this joint load, the individual case calculated above can simply be scaled up. In principle, each of the six DrMOS then sees the same thermal environment, the junction temperature is around 60 °C for all of them, the package tops are in the mid 40-degree range and the VRM zone on the PCB ends up in the low to mid 50-degree range. In reality, of course, these values are somewhat blurred because the heat flows of the six components overlap in the copper area and the DrMOS in the middle of the group usually run slightly warmer than those on the outside, but the order of magnitude remains the same.

The common consideration of the 24 watts in the PCB is thermally decisive. The copper area used in the VRM zone effectively forms a common node that is fed by all active components. If this zone is only connected to the rest of the board and to the cooler via a limited number of vias or relatively narrow copper paths, the effective R_board for the group increases and the local PCB temperature then rises above the approximately 52 °C mentioned. The same phenomenon can be seen at the heatsink, but with the opposite sign. The approximately 6 watts that are dissipated via the putties and package tops, together with the air temperature and the heat transfer of the cooler, define the 40 °C that you have set. In turn, the difference between the ambient air and these 40 °C can be used to calculate an effective R_sa of the air cooler.

The core statement remains the same for the evaluation of TIM performance. Even with several DrMOS in close packing and with an air cooler above the zone, around four-fifths of the waste heat is dissipated via the PCB and only around one-fifth via the upper path through the putty. Improving the putty or slightly reducing the layer thickness therefore only affects this partial path, which is still relevant in the steady state with six components, but the large shifts in hotspot temperatures are decided by the board design, the copper distribution, the via connection and the airflow of the cooler.

The interaction of more cooling and better thermal conductivity

I have calculated T_cool with 40, 35 and 30 °C as examples, which can be understood as rough steps of an increasing fan speed. The graph shows T_j over the pad thermal conductivity λ_pad for these three cooler temperatures. The curves run flat downwards: from 1 W/mK to around 3 W/mK, the better pad brings relatively much, beyond which the gain flattens out significantly. At the same time, the three curves are simply shifted by 10 K against each other if you change T_cool by 10 K. Since I tested this once with water, it should be roughly correct and transferable to the air cooler.

This means that the effect of a “better” pad can be classified very soberly. In this example, the jump from 3 to 6 W/mK only brings about 0.7 Kelvin at the junction at a heat sink temperature of 40 °C, while the jump from 6 to 11 W/mK brings about another 0.3 Kelvin. At the same time, reducing the heat sink temperature by 5 Kelvin practically lowers the junction temperature by the same 5 Kelvin, as the entire resistance branch is lower.

A realistic increase in fan speed, which keeps the heatsink 5 Kelvin cooler, therefore has an order of magnitude greater effect than switching from a 6 W/mK pad to an 11 W/mK pad or putty!

The graph illustrates this beautifully. The three curves are almost parallel, and the distances between the curves for 30, 35 and 40 °C are constant and significantly greater than the distance along the curve caused by pad optimization. This is the main message:

In this typical DrMOS scenario, the coolant temperature has an almost linear effect on the junction temperature, while the increase in pad thermal conductivity above about 3 to 4 W/mK only has an effect in the tenth of a Kelvin range. The physical cause lies in the dominant serial resistances in the package and in the board path, which limit the effect of the pad to a small proportion of the entire thermal chain.

Understand everything? With the heatsink, this really means: a lot (air) helps a lot, but with the pad: a lot of money hardly helps at all, because anything above 6 W/mK really doesn’t help much, except empty coffers!