Thermal paste database version 3.0 – More accurate and practical data, a technology upgrade and well over 100 tested pastes

1 - Introduction, Overview and Upgrade 2 - CPU Temperatures with Headspreader 3 - CPU Temperatures without Headspreader (Direct Die) 4 - GPU Temperatures (Direct Die) 5 - Summary and Conclusion

Introduction and special features of the direct-die configuration

In the thermal evaluation, I make a conscious distinction between processors with a permanently integrated heatspreader and those where the heatspreader has been removed or which operate without a lid ex works, such as many notebook and embedded chips. In a direct die configuration, the entire copper nickel layer of the heatspreader is omitted, the internal TIM layer between the die and IHS is either not present at all or only plays a subordinate role. The silicon is located directly under the external thermal paste and the cooler, making the thermal resistance chain significantly shorter and more direct.

The internal representation of the structure shows that with Direct Die, only a few relevant sections act in series from the silicon, namely the thermal resistance of the die itself, that of the external TIM layer, that of the radiator base and finally the convective transition from the radiator to the water flowing through it. The classic heat spreader, including its internal TIM, is completely eliminated. As a result, the relative share of the external paste in the total resistance shifts noticeably upwards; the paste is no longer a small link in a long chain, but one of the dominant parts of the total resistance. At the same time, however, it remains the case that the entire path into the water must be considered, i.e. including convection on the fluid side. The measurements and evaluations must therefore not only end at the contact die to cooler, but must also include the boundary conditions of the cooler, even if the chiller keeps the water temperature very stable at 30 °C.

Transparent calculation path with complete variables including convection

I present the calculation path for a direct die or notebook configuration in such a way that all relevant variables, including convection, are explicitly listed. The temperature is again calculated on the basis of the thermal resistances measured with TIMA, the water temperature is kept constant at T_Water = 30 °C with a laboratory chiller, so that the convective influences are transferred to a clearly defined boundary condition.

First, I define the variables for the electrical and thermal side

P_CPU in watts, real power dissipation of the CPU
T_Water in degrees Celsius, water temperature in the cooling circuit kept constant by the chiller
T_CPU in degrees Celsius, temperature directly on the silicon die on the surface
R_th,Die in Kelvin per Watt, thermal resistance of the silicon from the active area to the Die surface
R_th,TIM in Kelvin per Watt, external thermal resistance of the applied paste, measured with TIMA
R_th,Block in Kelvin per Watt, conductive resistance in the cooler base from the contact to the fluid side
R_th,convection in Kelvin per watt, convective contact resistance from the inside of the radiator to the water
R_th,cooler in Kelvin per watt, total resistance of the cooler from contact to water temperature
R_th,total in Kelvin per Watt, total sum of all serial partial resistances from the die to the water

The cooler resistance is made up of the conductive and convective components

R_th,convection = 1 / (h × A_fluid)
R_th,cooler = R_th,block R_th,convection

The total serial thermal resistance from the die to the water is therefore

R_th,ges = R_th,Die R_th,TIM R_th,Cooler

The temperature on the Die results from the usual relationship between power loss, total resistance and reference temperature of the fluid

T_CPU = T_water P_CPU × R_th,ges

In the practical implementation in the laboratory, this variable is not determined separately, but is converted into a quasi-constant boundary condition by using a powerful cooler with a defined volume flow and a laboratory chiller that regulates T_water stably at 30 °C. The variation between different pastes thus takes place at constant R_th,cooler and fixed T_water and concentrates primarily on the difference in R_th,TIM. For the external TIM, the relationship between layer thickness, thermal conductivity and surface area continues to apply

R_th,TIM = d / (λ × A_Die)

where d is the real BLT in meters, λ is the thermal conductivity in watts per meter and Kelvin and A_Die is the effective contact area of the bare chip in square meters. In practice, I replace this theoretical expression with the value R_th,TIM,measured with TIMA, which represents the actual contact conditions and the real BLT under pressure. The actual temperature calculation for different power points is then performed using the resistances R_th,Die, R_th,Cooler, which are constant for the setup, and R_th,TIM,measured, which varies depending on the paste. For the direct die scenarios, the same power levels are used as for the IHS CPU, except that the silicon is applied directly here. Here is an example with a CCD (Die) and 125 watts:

P_CPU,125 = 125 W
T_CPU,125 = T_Water P_CPU,125 × R_th,ges

In all cases, R_th,ges contains the proportion of the die, that of the TIM layer, that of the radiator base and the convective transition into the water. The differences between two pastes arise exclusively via the difference in R_th,TIM,measured, as R_th,die and R_th,cooler remain constant values in the identical setup. Notebook and embedded processors generally have smaller dies, so the effective contact area A_Die is smaller. As a result, the heat flux density q double line, defined as

q” = P_CPU / A_Die

The higher heat flux density places a greater burden on the TIM layer and convection; each additional Kelvin per watt in R_th,TIM or R_th,cooler has a significantly greater effect on T_CPU than with a large desktop IHS. This is precisely why differences in R_th,TIM are thermally much more visible in direct die, notebook and embedded chips, while the convective component is brought to a reproducible level by the defined water circuit and the stable volume flow.

Practical temperature evaluation based on complete resistance chains

We must now consider that the new, practical temperature calculation is only realistic for direct die and notebook or embedded chips if the complete resistance chain up to convection into the water is taken into account. The path does not physically end at the TIM layer, but in the cooling medium; the convective transition remains an indispensable part of the consideration. In the laboratory setup, this convective component is packed into a stable, reproducible R_th,cooler via the chiller, the defined volume flow and the geometry of the cooler, so that differences in the paste are not masked by fluctuating convection conditions.

Particularly with direct die configurations, but also with notebook and embedded platforms, the external TIM layer becomes a much more decisive link in the chain due to its smaller surface area and higher heat flux density. The calculation based on real measured R_th values of the TIMA system makes these effects transparent and allows pastes to be classified not only relative to each other, but also absolutely in relation to the expected Die temperature with a defined cooling concept and constant water temperature. This creates a consistent and reliable basis for translating the practical relevance of the measured thermal resistances directly into CPU temperatures without underestimating convection and the cooler side.

Which already gives us a gallant overview of the GPU problem, so please turn the page!