Foreword: Today it’s about technology, not patents
Before we get into the nitty-gritty, I would like to make one thing clear: Today will be exclusively about the technical aspects, not about patents or legal interpretations and quibbles. I cannot and do not want to answer such questions at this point, because they can hardly be resolved here and would only distract from the actual issue. The following article is a factual presentation of what I have already explained in the forum – without legal overtones, without personal evaluations and without any attempt to dispute anyone’s position. I am also not directly or actively involved in the product in any way with any of the companies involved, even if of course one or two technical comments have been made that could be reflected in certain details.
To really understand the topic of active balancing, it is not enough to take a superficial look and certainly not to repeat marketing-driven buzzwords. This is about physics, thermals, material ageing and current distribution, i.e. the fundamentals that make the difference between stable function and early failure. I find it quite amusing that in some forums there are initially loud criticisms that NVIDIA has not implemented balancing on its graphics cards, and only a few posts later the same principle is described as harmful or superfluous. The inconsistency speaks for itself – and it shows that there is a lack of sound understanding.
Therefore, this article is intended to take up the basics and transparently show where the ideal control range of an active balancing circuit actually lies, why this range is very narrow in practice, but decisive, and how such a control has a preventive effect against contact ageing and damage. I will also demonstrate mathematically at which currents an intervention becomes useful and which physical mechanisms in the connector play a role.
In essence, it’s about how a good load distribution can be implemented on the individual 12-volt lines, whether internally on the graphics card or externally, as with the already tested AMPINEL from aqua computer. The discussion about balancing does not just concern a piece of additional hardware, but the fundamental question of how modern high-current connections can be operated safely in ever more compact layouts. Anyone who understands these relationships quickly realizes that it is not a question of for or against, but of the technical necessity of getting unbalanced loads, contact resistances and ageing processes under control before they become critical.
What is possible on a graphics card: monitoring the currents
ASUS has, for example, implemented a remarkable current monitoring system on some higher-priced GeForce RTX 5090 (Astral/Matrix), which goes far beyond what is common on most graphics cards. According to the manufacturer, the card has a system with six low-impedance shunt resistors, which are located directly behind the 12V 2×6 connector and detect the individual 12-volt lines there. Each pin of the connector can therefore be monitored separately with regard to the current.

ASUS calls the whole thing “Power Detector” and advertises it with the information that a warning is issued per pin as soon as the current exceeds the permissible 9.2 amps. From a technical point of view, this is a considerable effort, which is clearly noticeable in the layout of the card. A precise shunt resistor is required for each wire, the measuring voltage of which is fed via separate Kelvin lines to analog current measuring amplifiers or directly to an A/D converter. These front ends must be located in the immediate vicinity of the current paths in order to avoid errors caused by track resistors, and they require a clean signal ground and a shielded connection to the evaluation electronics. The space required for such additional components alone is a challenge for modern GPUs with highly integrated VRM areas, as the areas around the connector are already overcrowded with inductors, capacitors and protective circuits. The front-end amplifiers must also be thermally stabilized and decoupled. Incorrect ground routing or interference from the VRM areas could falsify the measurement result, which is why the placement and routing must be carried out with exceptional care. ASUS has apparently solved this in such a way that the measurements are reliable enough not only to log, but also to trigger a specific protective reaction if they are exceeded.

The main benefit lies in direct diagnostics. The card recognizes in real time when one line is more heavily loaded than others and can immediately issue a warning or limit the power internally. This allows overheated contacts or uneven load distributions to be detected at an early stage before they cause thermal damage. Unlike external measuring systems, this control is fully integrated into the card logic. There are no communication delays, no additional plug connections and no external peripherals that would first have to process the signal. The manufacturer can integrate the measured values directly into the GPU firmware, define limit values and inform the user of deviating values in their own software interface.
The pure material costs for current monitoring on the graphics card are manageable. Six low-ohm shunt resistors in the milliohm range cost around EUR 1.5 per card, depending on tolerance and load capacity. The evaluation can be carried out either via dedicated current measurement ICs or via standard operational amplifiers, which costs an additional 2 to 3 euros. A 32-bit microcontroller unit with A/D converter and communication interface costs around EUR 1 to 2.50, but should already be available. The real effort is required for the firmware and integration. A simple implementation can be realized in a few weeks, but a fully developed series solution with calibration, telemetry and error detection requires several months of development time, which drives the costs much higher than the few components. Overall, the implementation of internal current monitoring for graphics cards would therefore be technically feasible and financially justifiable, but the limited space at the 12-volt input and the high layout density are the real hurdles, not the unit costs of the electronics or the implementation in the firmware.
However, ASUS has limited itself to pure monitoring without load shifting for good technical reasons. This means that the solution remains more elegantly integrated, but cannot compensate for asymmetrical currents. In an emergency, it only warns instead of taking countermeasures. Nevertheless, the concept has clear advantages: It is latency-free, requires no additional signal paths and offers the user complete transparency about the status of the power supply. However, the integration of such measuring circuits is not a trivial step. Shunt resistors generate heat loss, and even a few millikelvin difference can affect the measurement accuracy.
What is NOT feasible on a graphics card: Balancing the currents
Active load balancing directly on the circuit board of a modern graphics card is hardly practicable from a technical, thermal and manufacturing point of view. Even a brief look at the topology of current cards makes it clear that the power supply of a GPU today is not a monolithic system, but consists of many separate sub-supplies, all of which have different voltages, frequencies and phase positions. It would therefore be short-sighted to blame NVIDIA or the AIC alone for the lack of an integrated balancer or an internal protection circuit. Such systems simply cannot be practically implemented on a modern graphics card without rethinking the entire electrical architecture. The real core of the problem is therefore not on the board, but in front of it: in the connector itself.
NVIDIA could implement more sensors, telemetry or software warnings, but none of these would solve the mechanical and thermal problems of the connector. The board partners are also in a dilemma here: even with the highest manufacturing quality, micro-differences between pins, manufacturing tolerances of the socket and contact surface oxidation cannot be completely eliminated. Internal balancing would only postpone the problem, not solve it. It therefore remains to be said that the real weakness lies in the standard itself, i.e. in a connector that operates on the edge of what is physically sensible. It was adopted as a standard even though the current-carrying capacity of individual contacts and the thermal transitions are already critical in the optimum case. Any deterioration, for example due to uneven insertion, minimal dirt or material fatigue, can generate unbalanced loads that no circuit design on the card can prevent.
It would therefore be too cheap to blame NVIDIA or the board manufacturers for the lack of “symptom control”. They are merely reacting to the limitations of a specification that should never have been adopted in this form. The real source of the problem lies in the connector itself – a design that just about works under ideal conditions, but in practice punishes even the smallest deviations with disproportionate consequences.
Balancer between the 12V 2×6 header and the voltage converters
The first theoretical option would be to place the balancer directly behind the 12V connector – i.e. between the incoming lines of the 12V 2×6 connector and the high-current rails that lead into the actual voltage converters. Although this solution would have the charm of being directly at the source of the unbalanced load, it brings with it several fundamental problems. Firstly, this area is in close proximity to the actual regulation. Each downstream phase of a multiphase VRM system draws its currents dynamically according to the internal clock of the PWM controller, which operates at several hundred kilohertz. If an upstream electronic load sharing system intervenes in this current flow, additional voltage drops, phase shifts and leakage inductances occur, which severely disrupt the voltage converter control loops. This would introduce a “regulation before regulation” that has no knowledge of the control characteristics of the subsequent stages. At best, this can lead to oscillations; at worst, it destabilizes the entire power supply. Alternatively, further filtering and smoothing can be integrated. What makes sense externally and after further filters, resistors and at a certain distance is already highly sensitive in the immediate vicinity of the subsequent stages.
Added to this is electromagnetic compatibility. The currents coming out of the 12V connector are superimposed at high frequency, as the converters themselves operate in a highly pulsed manner. An additional MOSFET-based balancing stage with variable resistors would act as a broadband source of interference. Any change in the line resistance, even in the milliohm range, generates a non-linear voltage drop, which in turn feeds back into the control loops of the VRMs. The layout would have to provide additional ground planes, filters and decoupling to attenuate such interference – something that is physically almost impossible to implement in an area that is already fully occupied by high-current rails, sense lines and decoupling capacitors.
In addition, the power loss and heat dissipation speak against integration. Active balancing generally works with MOSFETs, which briefly dissipate power in the linear range in order to shift currents. With a load of 500 to 700 watts, an additional loss voltage of 50 millivolts on a line means a heat output of several watts, which would have to be dissipated over an area of a few square centimeters. This thermal load in the vicinity of the connector, i.e. in what is already the hottest zone of the card, would exceed the entire temperature budget.
Distribution of the lines to selected voltage regulators
A second theoretical option would be not to combine the six 12V lines in parallel, but to assign them specifically to individual voltage transformer groups in order to force a natural current distribution. In practice, however, this is impossible for several reasons. The power supply of a high-end GPU such as the RTX 5090 is divided into many independent voltage domains. In addition to the large main supplies such as NVVDD, MSVDD or FBVDD, there are smaller, dedicated rails through to various logic and I/O voltages. There are also secondary step-down converters that generate auxiliary voltages such as 5V, 1.8V or 0.95V from the 12V rail. Each of these domains has its own control loops, some even have their own PWM controllers and phase numbers. The currents are therefore not distributed evenly, but follow the dynamic load profile of the GPU, the memory, the signal paths and the peripherals.
A balancer that would couple each of the six 12V lines to a defined converter string would have to synchronously detect and regulate this multitude of different loads. This is not only complex in terms of control technology, but also clashes with the layout principle of modern graphics cards, in which all 12V paths converge in a low-impedance busbar in order to achieve symmetrical voltage ratios and minimal feedback. Splitting this busbar would divert the currents in unpredictable ways, disrupt the signal integrity of the sense lines and inevitably cause EMC problems. Each of these segments would also have to be individually fused and decoupled against crosstalk.
The production costs would also be considerable. The PCB layout would have to include additional copper layers for current isolation and filter routing, and the space required for MOSFETs, shunts, controllers and their thermal decoupling would increase the costs many times over. The validation of such designs would be extremely time-consuming, as every change to the current path would require complete recertification in accordance with EMC and safety standards. This would not be economically viable for mass production, where costs and installation space are crucial.
Consequently, the integration of an active load balancing system on the circuit board of a modern graphics card is technically conceivable, but practically incompatible with the existing architecture. Between the high packing density, the large number of separate supply rails, the sensitive control structures and the thermal and EMC-related restrictions, there is no scope for an additional, upstream control layer. An external solution, as implemented in the Ampinel, avoids precisely these problems by distributing the loads outside the board and only minimally changing the electrical structure of the current paths.
Interim conclusion
The only feasible internal variant on the graphics card is therefore a form of passive monitoring in which the currents of each line are measured individually, logged and reported if necessary. It provides diagnostic data, but does not interfere with the current flow. This method is space-saving, electrically transparent and can act as a supplement to the card’s protection logic, but is dependent on the responsiveness of the firmware. Active load distribution does not take place here, so the uniformity of the currents remains dependent on the physical state of the connector.




































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