ASRock X870E Taichi OCF Review and complete Teardown: Focus on the Essentials or more with less is almost impossible

1 - Introduction, unboxing and technical data 2 - Topology of voltage regulators and their cooling 3 - Teardown: USB 4 sub system, PC audio and WiFi 7 4 - Teardown: Chipset topology and other components 5 - Backplate, cooler, pads, and thermal conductivity 6 - UEFI, overclocking and own experience 7 - Performance and conclusion

The complete teardown of the ASRock X870E Taichi OCF now provides the necessary basis to evaluate the electrical topology, mechanical structure and thermal design not only theoretically, but also on the basis of real contact surfaces and material decisions. Only after the board has been completely dismantled can reliable statements be made about heat sink geometry, pad selection, pressure distribution, backplate function and the actual coupling between power stages, PCB and cooler. The aim of this teardown is therefore not just to show components, but to understand ASRock’s design decisions in detail and to classify them in the context of stability, continuous load and overclocking suitability, beyond marketing claims and pure specification lists.

I will now go through the analysis of the ASRock X870E Taichi OCF step by step and completely for the knowledge that results from the combination of layout, component selection and controller reality. It becomes very clear that a distinction must be made between the number of installed power stages and the actual number of controlled phases, even if this difference is often blurred in data sheets and marketing texts.

The starting point is ASRock’s usual, very clean PCB labeling. ASRock labels each individual power stage of the Vcore supply with PQVC1 to PQVC22 and the corresponding inductors accordingly with PLVC1 to PLVC22. In purely mechanical and assembly terms, there are therefore 22 voltage converter stages, each consisting of an integrated Smart Power Stage, an inductor and downstream output filtering. The power stages used are identical throughout the Vcore range and bear the identifier RAA2209004, i.e. 110 A PLCs from the Renesas environment.

However, this is where the decisive classification comes in. If you look at the PWM controllers used and their realistic capabilities, it quickly becomes clear that there cannot be 22 staggered control phases. There are simply no common digital PWM controllers that can control 22 real phases independently and interleaved. The controllers from the RAA2296xx family identified on the board are also within a range that is typical for eight to a maximum of ten phases per output. The conclusion that the board uses a so-called teaming topology is therefore obvious and technically sound.

In concrete terms, this means that the Vcore supply is designed as an 11-phase control system in which two identical Smart Power Stages work in parallel on one phase. These two PLCs are controlled synchronously and share the current without a time phase shift. Electrically, it therefore remains a single control phase, but on the thermal and current side it is a significantly reduced power stage. The PCB labeling up to PQVC22 makes perfect sense in this context, as ASRock numbers each individual power stage, not each control phase.

This design fits perfectly with the board’s objective. By parallelizing two 110 A power stages per phase, the current carrying capacity increases massively, while at the same time the losses per component are reduced and the thermal load is distributed very evenly. Even more important, however, is the control behavior. In contrast to classic phase doublers, which turn one phase into two staggered phases and thus introduce additional latency into the control loop, teaming remains extremely responsive. Especially with modern Ryzen CPUs with very steep load changes, this is a clear advantage for stability and overshoot behavior.

The associated inductors are logically grouped in pairs, even if they are mechanically designed individually. The sense lines of the Vcore supply are cleanly separated from the current-carrying copper surfaces and lead to the central PWM controller, where the voltage feedback is averaged phase by phase. This is supplemented by the telemetry of the Smart Power Stages themselves, which can record current and temperature. The evenly distributed 20K polymer capacitors behind the coils serve as local buffers and also support the control behavior during fast transients.

To the right of the socket is the SoC supply, clearly labeled as PQSOC1 to PQSOC4 and PLSOC1 to PLSOC4. This rail is designed as an independent four-phase regulation, also with fully discrete phases consisting of power stage, coil and output filtering. The spatial and electrical separation from the Vcore rail has been consistently implemented, which is particularly relevant for memory stability and infinity fabric operation. Sense and feedback lines are also separated here in order to minimize mutual interference.

The secondary and auxiliary rails, for example around PQMC, are also designed independently. The power stages used here have the identifier RAA220075R0 and belong to the smaller 75 A class. This suits their task as an auxiliary supply, where clean regulation and integrated protection mechanisms are more important than extreme current. The fact that ASRock also uses integrated Smart Power Stages here and does not rely on simple discrete MOSFET pairs underlines the claim to operate all relevant rails in a stable and well-monitored manner.

The memory-related power supply, identified on the PCB as PUMEM, is designed as a separate function block. Even if the specific IC cannot be clearly identified on the available images, it is clear that this is not another high-current PLC, but a control, monitoring or smaller regulator module for memory-relevant voltages. The placement close to the corresponding trace bundles and away from the Vcore hotspots indicates a deliberate decoupling.

The whole thing is controlled centrally via at least two digital PWM controllers. The RAA229628 acts as the main controller for the large phase banks, while the separately placed RAA229621 controls additional rails independently. Although this division increases the component complexity, it improves the decoupling of the power domains and thus the predictability of the behavior under overclocking and continuous load conditions.

The rear of the board with the massive backplate and the high proportion of via under the VRM zones show that ASRock has not cut corners thermally either. The dismantled VRM cooler confirms this impression. Each power stage is in full contact with thermal pads, the contact surfaces are evenly designed and the thermal mass is clearly designed for continuous load. There is no indication that individual stages are favored or neglected.

This results in a very coherent architecture. The Vcore supply consists of 11 real control phases, each with two 110 A smart power stages connected in parallel, supplemented by a separate four-phase SoC rail and further independent auxiliary rails. This is technically clean, electrically sensible and exactly the right decision for the intended purpose of a stable OC board. And at this point, you can allow yourself a slight smile. Perhaps it wouldn’t be a bad idea to occasionally remind the marketing team that a power stage is not yet a phase. The technology on the board is convincing enough, it doesn’t need inflated numbers to work.